1. Field of the Invention
The present invention relates to a semiconductor integrated circuit of the master slice system.
2. Description of the Background Art
A gate array of the master slice system is manufactured in the following manner: First, internal gate cells, in which elements such as transistors and resistors for forming gates are formed with no interconnection, are regularly arranged on a silicon chip in the form of an array, in a master step. Then, the transistors, the resistors and the like are appropriately interconnected with each other by metal contacts etc., in order to implement a desired integrated circuit, in a slice step. This integrated circuit is the gate array. Such a gate array has come into wide use in recent years, since steps of manufacturing the same can be reduced as compared with a conventional semiconductor integrated circuit.
FIG. 1 is an explanatory diagram showing typical structure of a general gate array. As shown in FIG. 1, N element areas 2 are provided along the column direction in a silicon chip region 1 on a slicon chip, while M internal gate cell parts 3 are provided in each element area 2 along the row direction. An interconnection area 4 is provided around each element area 2, for connecting the internal gate cell parts 3. An input/output buffer region 5 is provided around the interconnection areas 4 for electrical matching between the internal gate cell parts 3 of the gate array and an external device. Thus, the internal gate cell parts 3 are arranged in the form of an array of M rows and N columns.
FIG. 2 is a circuit diagram showing an example of an ECL (emitter coupled logic) type internal gate cell part 3 employing bipolar transistors. Referring to FIG. 2, transistors Q.sub.1 to Q.sub.5 and resistors R.sub.1 and R.sub.5 are formed in the internal gate cell part 3 by a prescribed pattern, in a master step. Physical pattern dimensions of these elements are so set that they are common to all of such internal gate cell parts 3, in the stage of designing the master, in consideration of performance and scale of the gates to be formed. When these elements Q.sub.1 to Q.sub.5 and R.sub.1 to R.sub.5 are interconnected as shown by dotted lines, for example, an OR circuit with inputs A and B and an output Y can be formed. Another circuit such as a two-input NOR circuit or an inverter can alternatively be formed by interconnecting the elements in a different manner. Symbol V.sub.BB indicates reference potential and symbol V.sub.EE indicates source voltage.
Thus, in a gate array of the master slice system, an integrated circuit can be manufactured in a short time, since necessary logic circuits can be formed by simply changing the manner of interconnection.
In the conventional semiconductor integrated circuit of the master slice system having the aforementioned structure, however, the degree of freedom is restricted in designing the operating speed of gates, since the elements forming the internal gate cell parts 3 are fixed in size.
In order to change the operating speed of the gates formed in the internal gate cell parts 3 as needed, spare transistors and resistors are formed in the internal gate cell parts 3. They are selected by interconnection, to make the operating speed variable. However, a gate array formed by arranging the internal gate cell parts 3 is considerably increased in area, due to formation of the spare transistors and resistors provided in the respective internal gate cell parts 3 for making the operating speed variable.
If the operating speed of the gates formed in the internal gate cell parts 3 is made variable in a small variable range, two types of gate arrays GA1 and GA2 of different operating speeds are connected as shown in FIG. 3. Referring to FIG. 3, element parts 6 and 7 are provided with various gates. The gate arrays GA1 and GA2 are connected through output buffers BF. For example, an ECL type gate array employed for a computer in practice utilizes a gate array of 1000 to 2000 gates having a gate delay time t.sub.pd of about 0.5 ns/gate and a gate array of 100 to 200 gates having a gate delay time t.sub.pd of about 0.2 ns/gate. Thus, a plurality of gate arrays are combined with each other depending on gate scales, operating speeds etc. In such structure, however, a large number of excessive input/output buffers BF are required for signal propagation from the element part 6 in the gate array GA1 to the element part 7 in the gate array GA2, to excessively increase power consumption.